A High-Speed S/H Circuit
Figure 20 shows a fast unity gain input buffer
(Si581) driving an SD5000 switch. One half of
the SD5000 is configured as dummy switches
for charge injection compensation. A JFET
output buffer minimizes droop. Transistors Q1
through Q4 level shift the ECL control input
signals into a voltage (referenced to the analog
signal voltage) used to drive the DMOS FETs.
G2
G3
Figure 17. Gate Control Signals for the SPDT
Switch Configuration
DAC Deglitcher
A very small charge injection makes DMOS
FETs excellent DAC deglitcher switches. Figure
21 illustrates a typical circuit configuration.
SD210
-5 V
Input 1
10 MHz
Shield
5V
15 V
0.047 µF
0.047 µF
Control
TTL
DG413
Output
Channel 1 On
SD210
-5 V
0.047 µF
Input 2
10 MHz
Shield
-5 V
0.047 µF
Channel 2 On
Figure 18. High Frequency SPDT Switch
Figure 19. Two 10-MHZ AM Modulated Outputs
for the SPDT Switch of Figure 18
10
Linear Integrated Systems, Inc.
●
4042 Clipper Ct.
●
Fremont, CA 94538
●
Tel: 510 490-9160
●
Fax: 510 353-0261
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