Principle of Operation
Figure 1 depicts an n-channel enhancement-
mode device with an insulated gate and
asymmetrical structure. The gate protection
Zener is shown with broken lines to indicate
that, although it is present on the chip, it is not a
main constituent of the fundamental switch
structure.
Gate
Protection
Zener
Asymmetrical
Structure
Insulated
Gate
Drain
Enhancement
Mode n-Channel
Body
Figure 1. DMOS Electrical System
The double-diffusion process creates a thin self-
aligning region of p-type material, isolating the
source from the drain region. The very short
channel length that results between the two
junction depths produces extremely low source-
to-drain and gate-to-drain capacitances at the
same time that it provides good breakdown
voltages.
When the gate potential is equal to or negative
with respect to the source, the switch is off. In
this state, the p-type material in the channel
forms two back-to-back diodes and prevents
channel conduction (Figure 3a). If a voltage is
applied between the S and D regions, only a
small junction leakage current will flow.
G
C
GS
C
GD
C
GS
+
Source
G
r
DS(on)
C
GD
S
+
D S
D
The DMOS field-effect transistor (FET) is
normally off when the gate-to-source voltage
(V
GS
) is 0 V. The lateral DMOS transistor,
shown in cross-section in Figure 2, has three
terminals (source, gate, and drain) on the top
surface and one (the body or substrate) on the
bottom. A Zener diode with a breakdown
voltage of approximately 40 V is added to
protect the gate against overvoltage and
electrostatic discharges.
Source
Oxide
Gate
Drain
(a) Off State
(b) On State
Figure 3. Equivalent Circuits
B
B
The silicon oxide insulation present between
gate and source forms a small capacitor that
accumulates charge.
If the gate-to-source potential (V
GS
) is made
positive, the capacitive effect attracts electrons
to the channel area immediately adjacent to gate
oxide. As V
GS
increases, the electron density in
the channel will exceed the hole density, and the
channel will become an n-type region. As the
channel conductivity is enhanced, the n-n-n
structure becomes a simple silicon resistor
through which current can easily flow in either
direction.
Figure 4 shows typical biasing for ±10 V analog
signal processing. Note that the drain is
2
n+
p-
p
n+
Channel
Body
Figure 2. Cross Sectional View of an Idealized
DMOS Structure
Linear Integrated Systems, Inc.
●
4042 Clipper Ct.
●
Fremont, CA 94538
●
Tel: 510 490-9160
●
Fax: 510 353-0261
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
