LTC1235
APPLICATIONS INFORMATION
Power Fail Warning
The LTC1235 generates a Power Failure Output (PFO) for
early warning of failure in the microprocessor’s power sup-
ply. This is accomplished by comparing the Power Failure
Input (PFI) with an internal 1.3V reference.
PFO
goes low
when the voltage at PFI pin is less than 1.3V. Typically
PFI is driven by an external voltage divider (R1 and R2 in
Figures 8 and 9) which senses either an unregulated DC
input or a regulated 5V output. The voltage divider ratio can
be chosen such that the voltage at PFI pin falls below 1.3V
several milliseconds before the +5V supply falls below the
maximum reset voltage threshold 4.75V.
PFO
is normally
used to interrupt the microprocessor to execute shutdown
procedure between
PFO
and
RESET
or RESET.
The power fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the
PFO
output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When
PFO
output is low, R3 sinks current from the sum-
ming junction at the PFI pin.
V
H
= 1.3V 1+
R1 R1
+
R2 R3
V
HYST
=
5V
R1
=
850mV
R3
R3 ≈ 5.88 R1
Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
7.5V = 1.3V 1+
51k (5V ± 1.3V)51k
±
1.3V(310k)
R2
R2 = 9.7k, Choose nearest 5% resistor 10k and recalculate
V
L
,
V
L
=1.3V
1+
V
H
=1.3V
1+
51k (5V ± 1.3V)51k
±
=
7.32V
1.3V(310k)
10k
51k 51k
+
=
8.151V
10k 300k
(7.32V – 6.25V)
=
10.7ms
100mV/ms
V
HYST
= 8.151V – 7.32V = 831mV
V
IN
≥ 7.5V
10μF
R1
51k
LT1086-5
V
IN
V
OUT
ADJ
+5V
When
PFO
output is high, the series combination of R3
and R4 source current into the PFI summing junction.
R1 (5V ± 1.3V)R1
V
L
=1.3V
1+ ±
R2 1.3V(R3+R4)
Assuming R4«R3,V
HYST
=
5V
R1
R3
+
+
V
CC
LTC1235
PFO
BACKUP
TO μP
100μF
R3
300k
0.1μF
R4
10k
PFI GND
R2
10k
1235 F08
Figure 8. Monitoring
Unregulated
DC Supply with the
LTC1235 Power Fail Comparator
V
IN
≥ 6.5V
LT1086-5
V
IN
V
OUT
ADJ
10μF
+5V
R1
27k
R4
10k
R3
2.7M
0.1μF
V
CC
LTC1235
PFO
BACKUP
PFI GND
TO μP
Example 1: The circuit in Figure 8 demonstrates the use
of the power fail comparator to monitor the unregulated
power supply input. Assuming the rate of decay of the
supply input V
IN
is 100mV/ms and the total time to execute
a shut-down procedure is 8ms. Also the noise of V
IN
is
200mV. With these assumptions in mind, we can reason-
ably set V
L
= 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage
of LT1086-5 (4.75V + 1.5V) and V
HYST
= 850mV.
+
10μF
+
R2
8.2k
R5
3.3k
1235 F09
Figure 9. Monitoring
Regulated
DC Supply with the
LTC1235 Power Fail Comparator
1235fa
12
LINER [ LINEAR TECHNOLOGY ]
