LTC1235
APPLICATIONS INFORMATION
Voltage Output
During normal operation, the LTC1235 uses a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to V
OUT
from V
CC
and has a typical on resistance
of 5. The V
OUT
pin should be bypassed with a capacitor of
0.1μF or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.
When operating currents larger than 50mA are required
from V
OUT
, or a lower dropout (V
CC
- V
OUT
voltage differ-
ential) is desired, the LTC1235 provides BATT ON output
to drive the base of external PNP transistor (Figure 3).
Another alternative to provide higher current is to connect
a high current Schottky diode from the V
CC
pin to the V
OUT
pin to supply the extra current.
ANY PNP POWER TRANSISTOR
the battery which can damage lithium batteries. LTC1235
uses a charge pumped NMOS power switch to eliminate
unwanted charging current while achieving low dropout
and low supply current. Since no current goes to the
substrate, the current collected by V
BATT
pin is strictly
junction leakage.
Conditional Battery Backup
LTC1235 provides an unique feature to either allow V
OUT
to
be switched to V
BATT
or to disable the CMOS RAM battery
backup function when primary power is lost. Disabling
the battery backup function is useful in conserving the
backup battery’s life when the SRAM doesn’t need battery
backup during long term storage of a computer system,
or delivery of the computer system to the end user.
The BACKUP pin (Pin 8) is used to serve this feature on
power-down. When V
CC
is falling through the reset volt-
age threshold, the status of the BACKUP pin (logic low
or logic high) is stored in the Memory Logic (see Block
Diagram). If the stored status is logic high and V
CC
fall to
50mV greater than V
BATT
, a 125Ω PMOS switch, M2, con-
nects the V
BATT
input to V
OUT
and the battery switchover
comparator, C2, shuts off the NMOS power switch, M1. M2
is designed for very low dropout voltage (input-to-output
differential). This feature is advantageous for low current
applications such as battery backup in CMOS RAM and
other low power CMOS circuitry. If the stored status is
logic low and V
CC
falls to 50mV greater than V
BATT
, the
Memory Logic keeps M2 off and C2 shuts off M1. V
OUT
is
in Battery Saving Mode (see Figure 4). The supply current
in both mode is 1μA maximum.
On power-ups, C2 keeps M1 off before V
CC
reaches 70mV
higher than V
BATT
. On the first power-up after the bat-
tery is replaced (with power off), the status stored in the
Memory Logic is undetermined. V
OUT
could be either in
Battery Backup Mode or in Battery Saving Mode. When
V
CC
is 70mV greater than V
BATT
, M1 connects V
OUT
to V
CC
.
C2 has typically 20mV of hysteresis to prevent spurious
switching when V
CC
remains nearly equal to V
BATT
and the
status stored in the Memory Logic is high. The response
time of C2 is approximately 20μs.
R1
BATT ON
V
OUT
V
CC
LTC1235
V
BATT
GND
1235 F03
+5V
0.1μF
0.1μF
+3V
Figure 3. Using BATT ON to Drive External PNP Transistor
The LTC1235 is protected for safe area operation with short
circuit limit. Output current is limited to approximately
200mA. If the device is overloaded for a long period of
time, thermal shutdown turns the power switch off until
the device cools down. The threshold temperature for
thermal shutdown is approximately 155°C with about 10°C
of hysteresis which prevents the device from oscillating
in and out of shutdown.
The PNP switch was not chosen for the internal power
switch because it injects unwanted current into the
substrate. This current is collected by the V
BATT
pin in
competitive devices and adds to the charging current of
1235fa
9
LINER [ LINEAR TECHNOLOGY ]
