PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
READ LATENCY
The READ latency is the delay in clock cycles, between the registration of
a READ command and the availability of the first bit of output data. The
latency can be set to 2 or 2.5 clocks.
If a READ command is registered at clock edge [n], and the latency is
[m] clocks, the data will be available by clock edge [n+m]. Table 2 indi-
cates the operating frequencies at which each CAS latency setting can
be used.
Reserved states should not be used as unknown operation or incompat-
ibility with future versions may result.
Table 2 - C
as
l
atency
Allowable Operating Frequency (MHz)
Speed
-10
-8
-75
-6
CAS Latency = 2
≤83
≤100
≤125
NA
CAS Latency = 2.5
≤100
≤125
≤133
≤166
OPERATING MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A
7
-A
12
, each set to zero, and bits A
0
-A
6
, set to the desired
values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A
7
and A
9
-A
12
, each set to zero, bit A
8
set to one, and bits A
0
-A
6
, set to
the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER command to select normal operating mode.
All other combinations of values for A
7
-A
12
are reserved for future use and/or test modes. Test modes and reserved states should not be used because
unknown operation or incompatibility from future versions may result.
EXTENDED MODE REGISTER
The EXTENDED MODE REGISTER controls functions beyond those controlled by the MODE REGISTER; these additional functions are DLL enable/disable,
output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 4. The EXTENDED MODE REGISTER command to the MODE
REGISTER (with BA
0
=1, BA
1
=0) and the register will retain the stored information until it is programmed again or the device realizes loss of power. The
enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the MODE REGISTER (BA
0
=BA
1
=LOW) to reset the DLL.
The EXTENDED MODE REGISTER must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
LOGIC Devices Incorporated
www.logicdevices.com
8
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
