PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
F
igure
3 - e
xtenDeD
m
oDe
r
egister
BA1
BA0
An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
n + 2 n + 1 n1 . . . 9 8 7 6
Operating Mode
0
1
5
4
3
2
1 0
DS DLL
Extended mode
register (Ex)
E0
Mn + 2 Mn + 1
0
0
1
1
0
1
0
1
Mode Register Definition
Base mode register
Extended mode register
Reserved
Reserved
2
E1
0
1
DLL
Enable
Disable
0
1
Drive Strength
Normal
Reduced
3
En . . . E9 E8 E7 E6 E5 E4 E3 E2 E1, E0
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Valid
–
Operating Mode
Reserved
Reserved
Notes:
1. n is the most significant row address bit.
.
2. The reduced drive strength option is available only on Design Revision F and K.
3. The QFC# option is not supported.
o
utPut
D
rive
s
trength
The normal full drive strength for all outputs are specified to be SSTL2,
Class II. The DDR IMOD supports an option for reduced drive. This option
is intended for the support of the lighter load and/or point-to-point environ-
ments. The selection of the reduced drive strength will alter the DQs and
DQSs from SSTL2, Class II drive strength to a reduced drive strength, which
is approximately 54% of the SSTL, Class II drive strength.
Dll e
naBle
/D
isaBle
The DLL must be enabled for normal operation. The DLL enable is required
during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debug or evaluation. When the
device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
LOGIC Devices Incorporated
www.logicdevices.com
11
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
