PreLIMINArY INforMAtIoN
L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
F
igure
1 - m
oDe
r
egister
D
eFinition
BA1 BA0 An . . .
A9 A 8 A7 A6 A5 A4 A3
A 2 A 1 A 0 Address bus
n+2
0
n+1
0
n1 . . .
9
8
7
6
5
4
3
2
1
0
Operating mode
CAS Latency BT Burst length
Mode register
(Mx)
Mn + 2 Mn + 1
0
0
1
1
0
1
0
1
Mode Register Definition
Base mode register
Extended mode register
Reserved
Reserved
M3
0
1
Burst Type
Sequential
Interleaved
M2 M1 M0 Burst Length
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Mn
0
0
–
. . . M9
0
0
–
0
0
–
M8
0
1
–
M7
0
0
–
M6–M0
Valid
Valid
–
Operating Mode
Normal operation
Normal operation/reset DLL
All other states reserved
M6
0
0
0
0
1
1
1
1
1
1
M5
0
0
1
1
0
0
1
1
M4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3 (-5B only)
Reserved
Reserved
2.5
Reserved
Note: 1. n is the most significant row address bit
LOGIC Devices Incorporated
www.logicdevices.com
9
High Performance, Integrated Memory Module Product
Feb 2, 2009 LDS-L9D112G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
