ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
STATE DIAGRAM
F
IGURE
2 - S
IMPLIFIED
S
TATE
D
IAGRAM
CKE L
Power
applied
Power
on
Reset
Procedure
Initialization
MRS, MPR,
write
leveling
SRE
MRS
SRX
Self
refresh
ZQCL
From any
state
RESET
ZQ
Calibration
ZQCL/ZQCS
REF
Idle
Refreshing
ACT
PDE
PDX
Active
Power-
Down
PDX
CKE L
PDE
Activating
Preharge
Power-
Down
CKE L
Bank
Active
WRITE
WRITE
WRITE AP
READ AP
READ
WRITE
READ
READ
Writing
Reading
WRITE AP
WRITE AP
READ AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Preharging
Automatic
Sequence
Command
Sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PREA=PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
LOGIC Devices Incorporated
www.logicdevices.com
4
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
LOGIC [ LOGIC DEVICES INCORPORATED ]
