88F6180-XX-BIR2C080 参数 Datasheet PDF下载

88F6180

Hardware Specifications

1.2.8

JTAG Interface Pin Assignment

Table 10: JTAG Pin Assignment

Pin Name

I/O

P in

Ty p e

CMOS

Power

R a il

VDDO

D e s c r i p t io n

JT_CLK

I

JTAG Clock

Clock input for the JTAG controller.

NOTE:

This pin is internally pulled down to 0.

JTAG Reset

When asserted, resets the JTAG controller.

NOTE:

This pin is internally pulled down to 0.

1

CPU JTAG Mode Select

Controls CPU JTAG controller state.

Sampled with the rising edge of JT_CLK.

NOTE:

This pin is internally pulled up to 1.

Core JTAG Mode Select

Controls the Core JTAG controller state.

Sampled with the rising edge of JT_CLK.

NOTE:

This pin is internally pulled up to 1.

JTAG Data Out

Driven on the falling edge of JT_CLK.

JTAG Data In

JTAG serial data input. Sampled with the JT_CLK rising edge.

NOTE:

This pin is internally pulled up to 1.

JT_RSTn

I

CMOS

VDDO

JT_TMS_CPU

I

CMOS

VDDO

JT_TMS_CORE

I

CMOS

VDDO

JT_TDO

O

CMOS

VDDO

JT_TDI

I

CMOS

VDDO

1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the

JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.

Doc. No. MV-S104988-U0 Rev. E

Page 28

Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary