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88F6180-XX-BIR2C080 参数 Datasheet PDF下载

88F6180-XX-BIR2C080图片预览
型号: 88F6180-XX-BIR2C080
PDF下载: 下载PDF文件 查看货源
内容描述: 集成控制器硬件规格 [Integrated Controller Hardware Specifications]
分类和应用: 控制器
文件页数/大小: 112 页 / 962 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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Pin and Signal Descriptions  
Pin Descriptions  
Table 7: Gigabit Ethernet Port Interface Pin Assignments  
Pin Name  
I/O  
Pin  
Type  
Power  
Rail  
Description  
GE_RXCLK  
I
CMOS  
VDD_GE  
RGMII Receive Clock  
The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz  
reference clock derived from the received data stream.  
MII/MMII Receive Clock  
Provides the timing reference for the reception of the receive  
data valid, receive error, and GE_RXD[3:0] signals. This clock  
operates at 2.5 MHz or 25 MHz.  
Copyright © 2008 Marvell  
Doc. No. MV-S104988-U0 Rev. E  
December 2, 2008, Preliminary  
Document Classification: Proprietary Information  
Page 25