88F6180
Hardware Specifications
1.2.5
Table 7:
Gigabit Ethernet Port Interface Pin Assignments
Gigabit Ethernet Port Interface Pin Assignments
I/O
P in
Ty p e
CMOS
Power
R a il
VDD_GE
D e s c r i p t io n
Pin Name
GE_TXCLKOUT
t/s
O
RGMII Transmit Clock
RGMII transmit reference output clock for GE_TXD[3:0] and
GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock.
MII/MMII Transmit Clock
MII/MMII transmit reference clock from PHY.
Provides the timing reference for the transmission of the MII
transmit clock, transmit enable, and GE_TXD[3:0] signals. This
clock operates at 2.5 MHz or 25 MHz.
I
GE_TXD[3:0]
t/s
O
CMOS
VDD_GE
RGMII Transmit Data
Contains the transmit data nibble outputs that run at double data
rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT
and bits [7:4] driven on the falling edge.
MII/MMII Transmit Data
Contains the transmit data nibble outputs that are synchronous
to the transmit clock input.
GE_TXCTL
t/s
O
CMOS
VDD_GE
RGMII Transmit Control
Transmit control synchronous to the GE_TXCLKOUT output
rising/falling edge.
GE_TXEN is driven on the rising edge of GE_TXCLKOUT.
A logical derivative of transmit enable and transmit error is driven
on the falling edge of GE_TXCLKOUT.
MII/MMII Transmit Error
It is synchronous to transmit clock.
Multiplexed on MPP
GE_RXD[3:0]
I
CMOS
VDD_GE
RGMII Receive Data
Contains the receive data nibble inputs that are synchronous to
GE_RXCLK input rising/falling edge.
MII/MMII Receive Data
Contains the receive data nibble inputs that are synchronous to
GE_RXCLK input.
GE_RXCTL
I
CMOS
VDD_GE
RGMII Receive Control
GE_RXCTL is presented on the rising edge of GE_RXCLK.
A logical derivative of receive data valid and receive data error is
presented on the falling edge of RXCLK.
MII/MMII Receive Data Valid
Doc. No. MV-S104988-U0 Rev. E
Page 24
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
