88F6180
Hardware Specifications
5
Clocking
lists the clocks in the 88F6180.
Table 25: 88F6180 Clocks
C l o ck Ty p e
CPU PLL
Description
Reference clock:
REF_CLK_XIN (25 MHz)
• Derivative clocks:
- CPU clock
- L2 cache clock
- DDR Clock (the Mbus-L uses the DDR clock.)
NOTE:
See
for CPU, L2 cache and
DDR frequency configuration.
L2 cache clock frequency must be equal or higher then DDR clock
frequency.
If the SSCG enable bit in the Sampled at Reset register is set, then the
SSCG circuit is applied for the CPU PLL reference clock (refer to the
Sampled at Reset register in the
88F6180, 88F6190, 88F6192, and
88F6281 Functional Specifications).
Core PLL
Reference clock:
REF_CLK_XIN (25 MHz)
• Derivative clocks:
- TCLK (core clock, 166 MHz)
- SDIO Clock (100 MHz)
- Gigabit Ethernet Clock (125 MHz)
- SPI clock (TCLK/30–TCLK/4 MHz)
- SMI clock (TCLK/128 MHz)
- TWSI clock (up to TCLK/1600)
NOTE:
See
for TCLK frequency
configuration.
There are two options for the reference clock configuration, depending on the PCI
Express clock 100 MHz differential clock:
• The device uses an external source for PCI Express clock. The PEX_CLK_P
pin is an input.
• The device uses an internal generated clock for PCI Express clock. The
PEX_CLK_P pin is an output, driving out the PCI Express differential clock.
•
Reference clock:
REF_CLK_XIN (25 MHz)
•
•
PEX PHY
USB PHY PLL
Doc. No. MV-S104988-U0 Rev. E
Page 46
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
