DA9078.003
28 January 2004
PAD LAYOUT
1702 µm
VSS RFI PDN AON DEC
MAS
1778 µm
9078Bx
VDD QO
QI
AGC OUT
DIE size = 1.70 x 1.78 mm; PAD size = 100 x 100
µm
Note:
Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or
left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component
assembly are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in the center of VDD pad
Note:
The on-chip product code 9078Bx identifies internal compensation capacitance option. x has values 1, 2,
3, 4 or 5 refering to capacitance option described in the Table 2 on page 4.
Pin Description
Power Supply Voltage
Quarz Filter Output
Quarz Filter Input
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down Input
Receiver Input
Power Supply Ground
Name
VDD
QO
QI
AGC
OUT
DEC
AON
PDN
RFI
VSS
X-coordinate
0
µm
306
µm
586
µm
866
µm
1109
µm
1109
µm
866
µm
549
µm
306
µm
16
µm
Y-coordinate
0
µm
19
µm
19
µm
19
µm
19
µm
1428
µm
1428
µm
1428
µm
1428
µm
1407
µm
Note
1
2
3
Notes:
1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1
µA
which is switched off at power down
3) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
2 (10)
MAS [ MICRO ANALOG SYSTEMS ]
