DA9078.003
28 January 2004
SAMPLES IN SBDIL 20 PACKAGE
NC
1
VDD 2
NC 3
QO 4
NC 5
QI 6
AGC 7
OUT 8
NC
9
NC 10
MAS9078
YYWW
XXXXX.X
20 VSS
19 NC
18 RFI
17 PDN
16 AON
15 DEC
14 NC
13 NC
12 NC
11 NC
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
PIN DESCRIPTION
Pin Name
NC
VDD
NC
QO
NC
QI
AGC
OUT
NC
NC
NC
NC
NC
NC
DEC
AON
PDN
RFI
NC
VSS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AI
AO
DO
Function
Positive Power Supply
Quartz Filter Output
1
Quartz Filter Input
AGC Capacitor
Receiver Output
Note
2
AO
DI
AI
AI
G
Demodulator Capacitor
AGC On Control
Power Down Input
Receiver Input
Power Supply Ground
3
4
Notes:
1) Pin 5 between quartz crystal filter pins must be connected to VSS to eliminate DIL package leadframe
parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1
µA
which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5 (10)
MAS [ MICRO ANALOG SYSTEMS ]
