4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
10. 33LV408 AC C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
= 3.3V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Data Hold from Write Time
-20
-25
-30
S
YMBOL
t
DH
S
UBGROUPS
9, 10, 11
0
0
0
--
--
--
M
IN
T
YP
33LV408
M
AX
--
--
--
U
NIT
ns
F
IGURE
1: T
IMING
W
AVEFORM OF
R
EAD
C
YCLE
(1)
Memory
F
IGURE
2: T
IMING
W
AVEFORM OF
R
EAD
C
YCLE
(2)
Read Cycle Notes:
1. WE is high for read cycle.
2. All read cycle timing is referenced form the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4.
5.
6.
At any given temperature and voltage condition, t
HZ(max)
is less than t
LZ(min)
both for a given device and from device to device.
Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
Device is continuously selected with CS = V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle.
04.02.04 REV 2
All data sheets are subject to change without notice
7
©2004 Maxwell Technologies
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
