4 Megabit (512K x 8-Bit) CMOS SRAM
F
IGURE
5: T
IMING
W
AVEFORM OF
W
RITE
C
YCLE
(3)
33LV408
Memory
W
RITE
C
YCLE
N
OTE
:
1.
2.
All write cycle timing is referenced from the last valid address to the first transition address.
A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and
WE going low: A write ends at the earliest transition among CS going high and WE going high. t is measured from begin-
ning of write to the end of write.
t is measured from the later of CS going low to end of write.
t is measured from the address valid to the beginning of write.
t is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high.
If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
D is the read data of the new address.
When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should
not be applied.
WP
CW
AS
WR
OUT
3.
4.
5.
6.
7.
8.
9.
10.
04.02.04 REV 2
All data sheets are subject to change without notice
9
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All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
