Programmable Skew Clock Buffer (PSCB)
O
PERATIONAL
M
ODE
D
ESCRIPTIONS
F
IGURE
5. Z
ERO
-S
KEW AND
/
OR
Z
ERO
-D
ELAY
C
LOCK
D
RIVER
7B991
Figure 5 shows the PSCB configured as a zero-skew clock buffer. In this mode, the 7B991 can be used as the basis
for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are
aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any
output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification,
coupled with the ability to drive terminated transmission lines (with impedances as low as 50
Ω
), allow efficient printed
circuit board design.
Memory
F
IGURE
6. P
ROGRAMMABLE
-S
KEW
C
LOCK
D
RIVE
Figure 6 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew
between outputs, the PSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs
can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small incre-
ments with the appropriate strapping of the function select pins. In this configuration, the 4Q0 output is fed back to FB
and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads
can receive the clock pulse at the same time.
In this illustration, the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL
synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase align-
ment.
09.23.02 Rev 4
All data sheets are subject to change without notice
11
©2002 Maxwell Technologies.
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MAXWELL [ MAXWELL TECHNOLOGIES ]
