Programmable Skew Clock Buffer (PSCB)
Test Mode
7B991
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the
7B991RP to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a remov-
able jumper to ground, or be tied LOW through a 100
Ω
resistor. This will allow an external tester to change the state
of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop discon-
nected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the
same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own
function select inputs (xF0 and xF1) and the waveform characteristics of the REF input.
Memory
09.23.02 Rev 4
All data sheets are subject to change without notice
10
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