7B991
Programmable Skew Clock Buffer (PSCB)
These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF
input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various por-
tions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-
skew characteristics described above at the same time. It can multiply by two and four or divide by two (and four) at
the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.
FIGURE 11. BOARD-TO-BOARD CLOCK DISTRIBUTION
Figure shows the 7B991 connected in series to construct a zero-skew clock distribution tree between boards. Delays
of the downstream clock buffers can be programmed to compensate for the wire length (i.e. select negative skew
equal to the wire delay) necessary to connect them to the master clock source, approximating a zerp-delay clock tree.
Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the
PLL filter. It is recommended that not more than two clock buffers be connected in series.
09.23.02 Rev 4
All data sheets are subject to change without notice 14
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