Programmable Skew Clock Buffer (PSCB)
T
ABLE
7. AC E
LECTRICAL
C
HARACTERISTICS
P
ARAMETER
Output HIGH Time Deviation from 50%
14,15
Output LOW Time Deviation from 50%
Output Rise Time
Output Fall Time
PLL Lock Time
17
Cycle-to-Cycle Output Jitter
Peak-to-
Peak
S
YMBOL
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
S
UBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
M
IN
--
--
0.15
0.15
--
--
1,2,3
7B991
T
YP
--
--
1.5
1.5
--
--
M
AX
3
3.5
2.5
2.5
0.5
200
U
NIT
ns
ns
ns
ns
ms
ps
(V
CC
= 5V ±10%, T
A
= -40
TO
85°C,
UNLESS OTHERWISE SPECIFIED
)
1. The level to be set of FS in determined by the “normal” operating frequency (f
NOM
) of the V
CO
and Time Unit Generator (see
Logic Block Diagram). Nominal frequency (f
NOM
) always appears at 1Q0 and the other outputs when they are operated in their
undivided modes (See Table 9). The frequency appearing at the REF and FB inputs will be f
NOM
when the output connected to
FB is undivided. The frequency of the REF and FB inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency
multiplication by using a divided output as the FB input.
2. Test measurement levels for the 7B991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or
less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
3. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
4. For all three state inputs. HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID indicates an open
connections. Internal termination circuitry holds an unconnected input to V
CC
/2.
5. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V
CC
has reached 4.3V.
6. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
U
delay
has been selected when all are loaded with 50 pF and terminated with 50
Ω
to 2.06V.
7. t
SKEWPR
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t
U
.
8. t
SKEW0
is defined as the skew between outputs when they are selected for 0t
U
. Other outputs are divided or inverted but not
shifted.
9. C
L
= 0 pF. For C
L
= 30 pF, t
SKEW0
= 0.35 ns.
10.There are three classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and
divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
11. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
ambient temperature, air
flow, etc.)
12.Guaranteed by design.
13.t
ODCV
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
spec-
ifications.
14.Specified with outputs loaded 30 pF for the 7B99 devices. Devices are terminated through 50
Ω
to 2.05V.
15.t
PWH
is measured at 2.0V. t
PWL
is measured at 0.8V.
16.t
ORISE
and t
OFALL
measured between 0.8V and 2.0V.
17.t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is
within specified limits.
Memory
09.23.02 Rev 4
All data sheets are subject to change without notice
6
©2002 Maxwell Technologies.
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
