欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX29F800TMC-90 参数 Datasheet PDF下载

MX29F800TMC-90图片预览
型号: MX29F800TMC-90
PDF下载: 下载PDF文件 查看货源
内容描述: 8M - BIT [ 1Mx8 / 512Kx16 ] CMOS FLASH MEMORY [8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 42 页 / 693 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
 浏览型号MX29F800TMC-90的Datasheet PDF文件第1页浏览型号MX29F800TMC-90的Datasheet PDF文件第2页浏览型号MX29F800TMC-90的Datasheet PDF文件第3页浏览型号MX29F800TMC-90的Datasheet PDF文件第4页浏览型号MX29F800TMC-90的Datasheet PDF文件第6页浏览型号MX29F800TMC-90的Datasheet PDF文件第7页浏览型号MX29F800TMC-90的Datasheet PDF文件第8页浏览型号MX29F800TMC-90的Datasheet PDF文件第9页  
MX29F800T/B
AUTOMATIC PROGRAMMING
The MX29F800T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at
room temperature of the MX29F800T/B is less than 8
seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will au-
tomatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F800T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished
in less than 8 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F800T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes al-
low sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically
programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.
P/N:PM0578
REV. 1.7, JUL. 24, 2001
5