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MX29F800TMC-90 参数 Datasheet PDF下载

MX29F800TMC-90图片预览
型号: MX29F800TMC-90
PDF下载: 下载PDF文件 查看货源
内容描述: 8M - BIT [ 1Mx8 / 512Kx16 ] CMOS FLASH MEMORY [8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 42 页 / 693 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
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MX29F800T/B
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the com-
mand register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system is not required to provide
any control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory
array(no erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE, whichever happens first pulse in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible while
the device resides in the target system. PROM pro-
grammers typically access signature codes by raising
A9 to a high voltage(VID). However, multiplexing high
voltage onto address lines is not generally desired sys-
tem design practice.
The MX29F800T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command reg-
ister. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of D6H/22D6H for MX29F800T, 58H/2258H
for MX29F800B.
TABLE 3. EXPANDED SILICON ID CODE
Pins
Manufacture code
Device code
for MX29F800T
Device code
for MX29F800B
Sector Protection
Verification
Byte
Byte
Byte
A0
Word VIL
VIL
VIH
VIH
X
X
Word VIH
Word VIH
A1
VIL
VIL
VIL
VIL
VIL
VIL
Q15~Q8 Q7 Q6 Q5
00H
X
22H
X
22H
X
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
Q4 Q3 Q2 Q1 Q0 Code(Hex)
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
00C2H
C2H
22D6H
D6H
2258H
58H
01H (Protected)
00H (Unprotected)
VIH X
VIH X
P/N:PM0578
REV. 1.7, JUL. 24, 2001
8