1Gb: x4, x8, x16 DDR3 SDRAM
Operations
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR,
ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of
the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or
REFRESH) are in progress. However, the power-down I
DD
specifications are not appli-
cable until such operations have been completed. Depending on the previous DRAM
state and the command issued prior to CKE going LOW, certain timing constraints must
be satisfied (as noted in Table 73). Timing diagrams detailing the different power-down
mode entry and exits are shown in Figure 98 on page 152 through Figure 107 on
Table 73:
Command to Power-Down Entry Parameters
Last Command Prior to
CKE LOW
1
ACTIVATE
PRECHARGE
READ or READAP
WRITE: BL8OTF, BL8MRS,
BC4OTF
WRITE: BC4MRS
WRITEAP: BL8OTF, BL8MRS,
BC4OTF
WRITEAP: BC4MRS
REFRESH
REFRESH
MODE REGISTER SET
Notes:
t
t
t
WRAPDEN
DRAM Status
Idle or active
Idle or active
Active
Active
Active
Active
Active
Idle
Power-down
Idle
Parameter (Min)
t
ACTPDEN
t
t
Parameter Value
1
t
CK
1
t
CK
RL + 4
t
CK + 1
t
CK
WL + 4
t
CK +
t
WR/
t
CK
WL + 2
t
CK +
t
WR/
t
CK
WL +
4
t
CK
+ WR +
1
t
CK
Figure
PRPDEN
RDPDEN
t
WRPDEN
WL + 2
t
CK + WR + 1
t
CK
REFPDEN
t
XPDLL
1
t
CK
Greater of 10
t
CK or 24ns
t
MRSPDEN
MOD
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchro-
nous
t
ANPD prior to CKE going LOW and remains asynchronous until
t
ANPD +
t
XPDLL after
CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until
t
CPDED has been satisfied,
at which time all specified input/output buffers will be disabled. The DLL should be in a
locked state when power-down is entered for the fastest power-down exit timing. If the
DLL is not locked during power-down entry, the DLL must be reset after exiting power-
down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down mode.
Precharge power-down mode must be programmed to exit with either a slow exit mode
or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in
slow exit mode or kept on in fast exit mode.
The DLL remains on when entering active power-down as well. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to “Asynchronous ODT Mode” on page 172 for detailed ODT usage requirements in slow
exit mode precharge power-down. A summary of the two power-down modes is listed in
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
151
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©2006 Micron Technology, Inc. All rights reserved.
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