1Gb: x4, x8, x16 DDR3 SDRAM
On-Die Termination (ODT)
Table 75:
Truth Table – ODT (Nominal)
Note 1 applies to the entire table
MR1[9, 6, 2]
000
000
000–101
000–101
110 and 111
Notes:
ODT Pin
0
1
0
1
X
DRAM Termination State
R
TT
_
NOM
disabled, ODT off
R
TT
_
NOM
disabled, ODT on
R
TT
_
NOM
enabled, ODT off
R
TT
_
NOM
enabled, ODT on
R
TT
_
NOM
reserved, ODT on or off
DRAM State
Any valid
Any valid except self refresh, read
Any valid
Any valid except self refresh, read
Illegal
Notes
1. Assumes dynamic ODT is disabled (see "Dynamic ODT" on page 162 when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal to
have it off during writes.
3. ODT must be disabled during reads. The R
TT
_
NOM
value is restricted during writes. Dynamic
ODT is applicable if enabled.
Nominal ODT resistance R
TT
_
NOM
is defined by MR1[9, 6, 2], as shown in Figure 47 on
TT
_
NOM
termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple R
TT
_
NOM
values based on RZQ/n where
n
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. R
TT
_
NOM
termination is allowed any time after
the DRAM is initialized, calibrated, and not performing read access or when it is not in
self refresh mode.
Write accesses use R
TT
_
NOM
if dynamic ODT (R
TT
_
WR
) is disabled. If R
TT
_
NOM
is used
during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 78 on page 163).
ODT timings are summarized in Table 76, as well as listed in Table 53 on page 67.
Examples of nominal ODT timing are shown in conjunction with the synchronous mode
of operation in “Synchronous ODT Mode” on page 167.
Table 76:
Symbol
ODTL on
ODTL off
t
AONPD
t
AOFPD
ODT Parameter
Description
ODT synchronous turn on delay
ODT synchronous turn off delay
ODT asynchronous turn on delay
ODT asynchronous turn off delay
ODT minimum HIGH time after ODT
assertion or write (BC4)
ODT minimum HIGH time after
write (BL8)
ODT turn-on relative to ODTL on
completion
ODT turn-off relative to ODTL off
completion
Begins at
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
Defined to
R
TT
_
ON
±
t
AON
R
TT
_
OFF
±
t
AOF
R
TT
_
ON
R
TT
_
OFF
Definition for All
DDR3 Speed Bins
CWL + AL - 2
CWL + AL - 2
1–9
1–9
4
t
CK
Units
t
CK
t
CK
ns
ns
t
ODTH4
ODT registered HIGH ODT registered
or write registration
LOW
with ODT HIGH
Write registration
with ODT HIGH
Completion of
ODTL on
Completion of
ODTL off
ODT registered
LOW
R
TT
_
ON
R
TT
_
OFF
CK
ODTH8
t
AON
t
AOF
6
t
CK
See Table 53 on
0.5
t
CK ± 0.2
t
CK
t
CK
ps
t
CK
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1Gb_DDR3_5.fm - Rev. D 8/1/08 EN
161
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