ML2724
entered beginning with the MSB (“big-endian”). The word is divided into a leading 14-bit data field followed by a 2-bit
address field. When the address field has been decoded the destination register is loaded on the rising edge of EN.
Providing less than 16 bits of data will result in unpredictable behavior when EN goes high.
Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift
register on the rising edge of the CLK pin. This information is loaded into the target control register when EN goes high.
This serial interface bus is similar to that commonly found on PLL devices. It can be efficiently programmed by either
byte or 16-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal power
when the bus is inactive. Refer to Figure 4 and Table 2: 3-Wire Bus Timing Characteristics for timing and register
programming illustrations.
SYMBOL PARAMETER
BUS CLOCK (CLK)
MIN
TYP
MAX
UNIT
tr
CLK input rise time
CLK input fall time
CLK period
15
15
Ns
Ns
Ns
tf
tck
50
ENABLE (EN)
tew
tl
Minimum pulse width
100
15
Ns
Ns
Ns
Delay from last CLK rising edge
Set up time to ignore next rising CLK
tse
15
BUS DATA (DATA)
ts
th
data to clock set up time
data to clock hold time
15
15
Ns
Ns
Table 2: 3-Wire Bus Timing Characteristics
t
F
t
t
t
S
t
CK
R
L
t
H
CLK
DATA
EN
LSB
MSB
t
EW
ADDRESS
DATA
Figure 4: Serial Bus Timing for Address and Data Programming
DS2724-F-01
FINAL DATASHEET
APRIL 2003
16
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
