ML2724
Receiver data low-pass filter bandwidth
Transmit data low-pass filter bandwidth
TRANSMIT MODE
In TRANSMIT mode, the PLL is closed to eliminate frequency drift. A two-port modulator modulates both the VCO and
the fractional-N PLL. The VCO is directly modulated with filtered FSK transmit data. The PLL is driven by a sigma-delta
modulator, which ensures that the PLL follows the mean frequency of the modulated VCO.
The transmit modulation filter is automatically tuned during every RECEIVE time, alleviating the need for production
alignment. Asserting RXON enables the ML2724. The rising edge of XCEN triggers a complete calibration of all the on-
chip filters, which takes up to 256
µ
s, which ensures the modulation filters are aligned to prevent unwanted spurious
emissions.
PLL PROGRAMMING & CHANNEL SELECTION
The ML2724 PLL is programmed via control register 2 to the set RF center frequency of operation of the radio. The PLL
does not need to be (though it can be) reprogrammed between RECEIVE and TRANSMIT modes. Nominal channel
separation is 2.048MHz, allowing for over 40 non-overlapping channels in any given location. With careful planning,
channels can be programmed in 1024kHz steps as long as care is exercised to insure that two radio links will not share
spectrum at any one time. The equation to determine channel center frequency from the ML2724 control register word
is:
f
C
= CHQ<0:11>*1.024 MHz
STANDBY MODE
In STANDBY mode, the ML2724 transceiver is powered down. The only circuits active are the control interfaces, which
are digital CMOS to minimize power consumption. The serial control interface and control registers remain powered up
and will accept and retain programming data as long as the digital supply is present. When exiting STANDBY mode, the
device may need to be kept in RECEIVE mode for up to 256
µ
s to allow for filter self-calibration.
TEST MODE
The RF to digital functionality of the ML2724 requires special test mode circuitry for IC production test and radio
debugging. A test register, accessible via the 3-wire serial interface, controls the test multiplexers. (See
).
DATA INTERFACE
There are two control interfaces: CONTROL and SERIAL.
CONTROL INTERFACE
The control interface provides immediate control and monitoring of the ML2724. Input signals include:
XCEN:
RXON:
FREF:
Transceiver enable. Places the ML2724 in Standby or Active (when asserted) modes.
Receive On. Places an Active ML2724 in Receive mode when asserted.
Reference frequency input
Received Signal Strength Indicator: indicates the power of the received signal
External Power Amplifier Control Pin
Output signals include:
RSSI:
PAON:
SERIAL INTERFACE
A 3-wire serial interface (EN, DATA, CLK) is used for programming the ML2724 configuration registers, which control
device mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are
DS2724-F-01
FINAL DATASHEET
APRIL 2003
15
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
