ML2724
NAME
DESCRIPTION
DEFINITION
Reserved
Reserved
Reserved
Reserved
RCLP
Reserved
Reserved
Set all bits to 0 (zero)
Reserved
Reserved
RSSI Clip Disable
0: RSSI clipped to 1.9V at –15dBm
1: RSSI not clipped
LVLO
Low Voltage Lockout
0: PAON Undisturbed
1: PAON De-asserted for VCCA<2.65V. Reset on RXON high
Set to 0
Reserved
TXM
Reserved
TX RF Output Mode
0: TX RF Output always on in TX mode
1: TX RF Output follows PAON signal
TPC
Transmit Power Control
Transmit Test Mode
0: AOUT pin pulled to ground
1: AOUT pin high impedance
TXCW
0: FSK modulation in Transmit mode
1: CW (no modulation in Transmit mode)
Reserved
AOUT
Reserved
Set to 0
Analog Output
0: AOUT pin is Transmit Power Control
1: AOUT pin is Analog Data Out
RD0
QPP
Reference Frequency Select
PLL Charge Pump Polarity
0: 6.144MHz nominal reference frequency
1: 12.288MHz nominal reference frequency (preferred)
0: For fc < fref, charge pump sources current
1: For fc < fref, charge pump sinks current
ADR1
ADR0
MSB Address Bit
LSB Address Bit
ADR1=0
ADR0=0
Table 3: Register 0 -- PLL Configuration Register
NAME
DESCRIPTION
DEFINITION
Reserved
Reserved
CHQ11
CHQ10
CHQ9
CHQ8
CHQ7
CHQ6
CHQ5
CHQ4
CHQ3
CHQ2
CHQ1
CHQ0
ADR1
Set all bits to 0 (zero)
Channel Frequency select bits
Divide ratio=fc/1.024
MSB Address Bit
LSB Address Bit
ADR1=0
ADR0=1
ADR0
Table 4: Register 1 – Channel Frequency Register
DS2724-F-01
FINAL DATASHEET
APRIL 2003
18
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
