M25P20 Serial Flash Embedded Memory
Operating Features
Status Register
The status register contains a number of status and control bits that can be read or set
(as appropriate) by specific commands. For a detailed description of the status register
bits, see the READ STATUS REGISTER command.
Data Protection by Protocol
Non-volatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power on reset and an internal timer (t
PUW
) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
PROGRAM, ERASE, and WRITE STATUS REGISTER commands are checked before they
are accepted for execution to ensure they consist of a number of clock pulses that is a
multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit.
In addition to the low power consumption feature, the DEEP POWER-DOWN mode of-
fers extra software protection since all WRITE, PROGRAM, and ERASE commands are
ignored when the device is in this mode.
Software Data Protection
Memory can be configured as read-only using the block protect bits (BP1, BP0) as
shown in the Protected Area Sizes table.
Hardware Data Protection
Hardware data protection is implemented using the write protect signal applied on the
W# pin. This freezes the status register in a read-only mode. In this mode, the block pro-
tect (BP) bits and the status register write disable bit (SRWD) are protected.
Table 3: Protected Area Sizes
Status Register Content
BP Bit 1
0
0
1
1
BP Bit 0
0
1
0
1
Note:
none
Upper 4th (sector 3)
Upper half (sectors 2 and 3)
All sectors (sectors 0 to 3)
Protected Area
Memory Content
Unprotected Area
All sectors (sectors 0 to 3)
Lower 3/4ths (sectors 0 to 2)
Lower half (sectors 0 and 1)
none
1. 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command
only if all block protect bits (BP1, BP0) are 0.
Hold Condition
The HOLD# signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal LOW does not terminate
any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.
PDF: 09005aef8456656e
m25p20.pdf - Rev. A 2/13 EN
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