M25P20 Serial Flash Embedded Memory
SPI Modes
Figure 4: Bus Master and Memory Devices on the SPI Bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
SPI Bus Master
DQ1 DQ0
VCC
VSS
C
DQ1
DQ0
VCC
VSS
C
DQ1 DQ0
VCC
VSS
R
CS3
CS2
CS1
S#
SPI memory
device
R
SPI memory
device
R
SPI memory
device
W#
HOLD#
S#
W#
HOLD#
S#
W#
HOLD#
Notes:
1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.
2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the
S# line HIGH-Z.
3. The bus master may enter a state where all I/O are HIGH-Z at the same time; for exam-
ple, when the bus master is reset. Therefore, C must be connected to an external pull-
down resistor so that when all I/O are HIGH-Z, S# is pulled HIGH while C is pulled LOW.
This ensures that S# and C do not go HIGH at the same time and that the
t
SHCH require-
ment is met.
4. The typical value of R is 100 kΩ, assuming that the time constant R × C
p
(C
p
= parasitic
capacitance of the bus line) is shorter than the time during which the bus master leaves
the SPI bus HIGH-Z.
5. Example: Given that C
p
= 50 pF (R × C
p
= 5μs),
the application must ensure that the bus
master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs.
PDF: 09005aef8456656e
m25p20.pdf - Rev. A 2/13 EN
9
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2012 Micron Technology, Inc. All rights reserved.
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