8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled
to check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation outputs the status register
contents on DQ0–DQ7 without prior command. While
the status register contents are read, the outputs are not
be updated if there is a change in the ISM status unless
OE# or CE# is toggled. If the device is not in the write,
erase, erase suspend or status register read mode, READ
STATUS REGISTER (70h) can be issued to view the status
register contents.
All of the defined bits are set by the ISM, but only
the ISM and erase suspend status bits are reset by the
ISM. The erase, write and V
PP
status bits must be cleared
using CLEAR STATUS REGISTER. If the V
PP
status bit
(SR3) is set, the CEL does not allow further WRITE or
ERASE operations until the status register is cleared.
This enables the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before check-
ing the status register instead of checking after each
individual WRITE. Asserting the RP# signal or power-
ing down the device also clears the status register.
Table 2
Status Register Bit Definitions
ISMS
7
ESS
6
ES
5
WS
4
V
PP
S
3
R
2–0
STATUS
BIT #
SR7
STATUS REGISTER BIT
ISM STATUS (ISMS)
1 = Ready
0 = Busy
ERASE SUSPEND STATUS (ESS)
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS (ES)
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS (WS)
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE
V
PP
STATUS (V
PP
S)
1 = No V
PP
voltage detected
0 = V
PP
present
RESERVED
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
bit to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode
and sets this and the ISMS bit to “1.” The ESS bit remains “1”
until an ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
V
PP
S detects the presence of a V
PP
voltage. It does not monitor V
PP
continuously, nor does it indicate a valid V
PP
voltage. The V
PP
pin
is sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.
V
PP
S must be cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
SR6
SR5
SR4
SR3
SR0-2
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
