8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F800B3 and MT28F008B3 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to V
SS
±0.2V. In this mode, the current
draw is a maximum of 8µA at 3.3V V
CC
. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.
tion is block-oriented. All READ and WRITE operations
are done on a random-access basis.
The boot block is protected from unintentional ERASE
or WRITE with a hardware protection circuit which re-
quires that a super-voltage be applied to RP# or that the
WP# pin be driven HIGH before erasure is commenced.
The boot block is intended for the core firmware required
for basic system functionality. The remaining ten blocks
do not require that either of these two conditions be met
before WRITE or ERASE operations.
BOOT BLOCK
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage (V
HH
)
of 12V or when the WP# pin is HIGH. During a WRITE or
ERASE of the boot block, the RP# pin must be held at V
HH
or the WP# pin held HIGH until the WRITE or ERASE is
completed. (The WP# pin does not apply to the SOP
package.) The V
PP
pin must be at V
PPH
(3.3V or 5V) when
the boot block is written to or erased.
MEMORY ARCHITECTURE
The MT28F800B3 and MT28F008B3 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather than
the entire array are erased, total device endurance is
enhanced, as is system flexibility. Only the ERASE func-
Figure 1
Memory Address Maps
WORD ADDRESS
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
BYTE ADDRESS
FFFFFh
WORD ADDRESS
7FFFFh
BYTE ADDRESS
FFFFFh
128KB Main Block
E0000h
DFFFFh
16KB Boot Block
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
70000h
6FFFFh
FC000h
FBFFFh
FA000h
F9FFFh
F8000h
F7FFFh
E0000h
DFFFFh
128KB Main Block
C0000h
BFFFFh
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
A0000h
9FFFFh
128KB Main Block
80000h
7FFFFh
60000h
5FFFFh
C0000h
BFFFFh
128KB Main Block
60000h
5FFFFh
128KB Main Block
50000h
4FFFFh
A0000h
9FFFFh
128KB Main Block
40000h
3FFFFh
128KB Main Block
40000h
3FFFFh
80000h
7FFFFh
128KB Main Block
20000h
1FFFFh
128KB Main Block
30000h
2FFFFh
60000h
5FFFFh
96KB Main Block
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
128KB Main Block
20000h
1FFFFh
10000h
0FFFFh
00000h
40000h
3FFFFh
8KB Parameter Block
8KB Parameter Block
16KB Boot Block
128KB Main Block
20000h
1FFFFh
128KB Main Block
00000h
Bottom Boot
MT28F008B3/800B3xx-xxB
Top Boot
MT28F008B3/800B3xx-xxT
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
