8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F800B3 and MT28F008B3 Flash devices in-
corporate a number of features ideally suited for system
firmware. The memory array is segmented into indi-
vidual erase blocks. Each block may be erased without
affecting data stored in other blocks. These memory
blocks are read, written and erased with commands to
the command execution logic (CEL). The CEL controls
the operation of the internal state machine (ISM), which
completely controls all WRITE, BLOCK ERASE and VERIFY
operations. The ISM protects each memory location from
over-erasure and optimizes each memory location for
maximum data retention. In addition, the ISM greatly
simplifies the control necessary for writing the device in-
system or in an external programmer.
The Functional Description provides detailed infor-
mation on the operation of the MT28F800B3 and
MT28F008B3 and is organized into these sections:
•
•
•
•
•
•
•
•
•
•
•
Overview
Memory Architecture
Output (READ) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
WRITE/ERASE Cycle Endurance
Power Usage
Power-Up
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or
written only when the RP# pin is taken to V
HH
or when the
WP# pin is brought HIGH. (The WP# pin does not apply to
the SOP package.) This provides additional security for
the core firmware during in-system firmware updates
should an unintentional power fluctuation or system
reset occur. The MT28F800B3 and MT28F008B3 are avail-
able with the boot block starting at the bottom of the
address space (“B” suffix) and the top of the address
space (“T” suffix).
SELECTABLE BUS SIZE (MT28F800B3)
The MT28F800B3 allows selection of an 8-bit
(1 Meg x 8) or 16-bit (512K x 16) data bus for reading and
writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is read
or written only on the lower eight bits (DQ0–DQ7).
Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written in
word form.
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures protec-
tion against overerasure and optimizes write margin to
each cell.
During WRITE operations, the ISM automatically in-
crements and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When BLOCK ERASE is performed, the ISM au-
tomatically overwrites the entire addressed block (elimi-
nates overerasure), increments and monitors ERASE at-
tempts, and sets bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register enables an external processor
to monitor the status of the ISM during WRITE and ERASE
operations. Two bits of the 8-bit status register are set and
cleared entirely by the ISM. These bits indicate whether
the ISM is busy with an ERASE or WRITE task and when an
ERASE has been suspended. Additional error informa-
tion is set in three other bits: V
PP
status, write status and
erase status.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
OVERVIEW
SMART 3 TECHNOLOGY (B3)
Smart 3 operation allows maximum flexibility for in-
system READ, WRITE and ERASE operations. WRITE and
ERASE operations may be executed with a V
PP
voltage of
3.3V or 5V. Due to process technology advances, 5V V
PP
is
optimal for application and production programming.
ELEVEN INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F800B3 and MT28F008B3 are organized into
eleven independently erasable memory blocks that al-
low portions of the memory to be erased without affect-
ing the rest of the memory data. A special boot block is
hardware-protected against inadvertent erasure or writ-
ing by requiring either a super-voltage on the RP# pin or
driving the WP# pin HIGH. (The WP# pin does not apply
to the SOP package.) One of these two conditions must
exist along with the V
PP
voltage (3.3V or 5V) on the V
PP
pin
before a WRITE or ERASE is performed on the boot
block. The remaining blocks require that only the V
PP
voltage be present on the V
PP
pin before writing or
erasing.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
