8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL
43
9
11
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
PP
=
V
PPH
1
(3.3V) or V
PPH
2
(5V) and RP# = V
IH
during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at V
HH
(12V), and must be held at V
IH
during all
other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all
data is accessed through DQ0–DQ7. DQ15/(A - 1) becomes the
least significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F800B3) to allow for a selection of an 8-
bit byte from the 1,048,576 available.
–
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
33
24
–
28
47
OE#
BYTE#
Input
Input
11, 10, 9, 8,
7, 6, 5, 4, 42,
41, 40, 39,
38, 37, 36,
35, 34, 3, 2
31
21, 20, 19, 18,
17, 16, 15, 14,
8, 7, 36, 6, 5,
4, 3, 2, 1, 40,
13, 37
–
25, 24, 23,
22, 21, 20,
19, 18, 8, 7,
6, 5, 4, 3, 2,
1, 48, 17, 16
45
A0–A18/
(A19)
Input
DQ15/
(A - 1)
DQ0–
DQ7
DQ8–
DQ14
V
PP
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
Output of address input when BYTE# = LOW during READ or WRITE
operation.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to input
commands to the CEL.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, V
PP
must be at V
PPH
1
(3.3V) or V
PPH
2
(5V). V
PP
= “Don’t Care” during all other
operations.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
–
No Connect: These pins may be driven or left unconnected.
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
25, 26, 27,
28, 32, 33,
34, 35
–
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
11
23
13, 32
–
30, 31
23, 39
29, 38
37
27, 46
9, 10, 15
V
CC
V
SS
NC
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
