ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
TABLE OF CONTENTS
Functional Block Diagram – 4 Meg x 16 ...............
– 2 Meg x 32 ...............
Pin and Ball Descriptions .......................................
SDRAM Interface Functional Description
.......
Initialization ......................................................
Register Definition .............................................
Mode Register ..............................................
Burst Length ............................................
Burst Type ...............................................
CAS Latency ............................................
Operating Mode .....................................
Write Burst Mode ...................................
Commands ........................................................
Truth Table 2a (Harware Command
Sequences [HCS]) .................................................
Truth Table 2b (Software Command
Sequences [SCS]) ..................................................
5
6
7
10
10
10
10
10
12
12
12
12
13
Truth Table 1 (Commands and DQM Operation) ........
13
14
15
18
18
18
18
18
18
18
18
18
19
19
20
25
25
25
25
26
27
28
29
30
30
30
30
31
31
Command Inhibit ........................................
No Operation (NOP) ...................................
Load Mode Register .....................................
Active ............................................................
Read .............................................................
Write ............................................................
Active Terminate ..........................................
Burst Terminate ............................................
Load Command Register .............................
Operation ..........................................................
Bank/Row Activation ..................................
Reads ............................................................
Write Bursts ..................................................
Active Terminate ..........................................
Power-Down ................................................
Clock Suspend .............................................
Burst Read/Single Write ...............................
Truth Table 3 (CKE) ..................................................
Truth Table 4 (Current State, Same Bank) ..................
Truth Table 5 (Current State, Different Bank) .............
Command Execution Logic (CEL) ...............
Internal State Machine (ISM) ......................
ISM Status Register ......................................
Output (READ) Operations ..............................
Memory Array .............................................
Status Register ..............................................
Device Configuration Register .....................
Input Operations ..............................................
Memory Array .............................................
Command Execution ........................................
Status Register ..............................................
Device Configuration ..................................
Program Sequence .......................................
Erase Sequence .............................................
Program and Erase NVMode Register .........
Block Protect/Unprotect Sequence ..............
Device Protect Sequence ..............................
Chip Initialize Sequence ..............................
Disable LCR Sequence ..................................
Reset/Deep Power-Down Mode .......................
Error Handling ..................................................
Program/Erase Cycle Endurance .......................
Absolute Maximum Ratings .............................
DC Electrical Characteristics
and Operating Conditions ..........................
I
CC
Specifications and Conditions ....................
Capacitance .......................................................
Electrical Characteristics and Recommended
AC Operating Conditions (Timing Table) ..
AC Functional Characteristics ..........................
Timing Waveforms
Initialize and Load Mode Register
RP# ..............................................................
FCS ..............................................................
Clock Suspend Mode ........................................
Reads
Read .............................................................
Alternating Bank Read Accesses ..................
Full-Page Burst .............................................
DQM Operation ..........................................
Program/Erase
Bank
a
followed by READ to bank
a ..........
Bank a followed by READ to bank b ..........
31
31
31
32
33
33
33
33
33
33
33
34
34
34
34
35
35
35
36
36
36
36
45
45
46
46
47
48
49
50
51
52
53
54
55
56
57
Flash Memory Functional Description
............
Flash Command Sequences ..............................
Hardware Command Sequence (HCS) .......
Software Command Sequence (SCS) ..........
Memory Architecture ........................................
Protected Blocks ...........................................
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
