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MT44K16M36 参数 Datasheet PDF下载

MT44K16M36图片预览
型号: MT44K16M36
PDF下载: 下载PDF文件 查看货源
内容描述: 576MB : X18 , X36 RLDRAM 3 [576Mb: x18, x36 RLDRAM 3]
分类和应用: 动态存储器
文件页数/大小: 111 页 / 6205 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Advance
576Mb: x18, x36 RLDRAM 3
Mirror Function
Mirror Function
The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple
dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command
balls are in their true layout. If the MF ball is tied HIGH, the address and command balls
are mirrored around the central y-axis (column 7). The following table shows the ball
assignments when the MF ball is tied HIGH for a x18 device. Compare that table to Ta-
are mirrored on the x36 device.
Table 41: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH
1
A
B
C
D
E
F
G
H
J
K
L
M
N
V
EXT
V
DD
A13
V
SS
A9
V
SS
A10
V
DDQ
NF
V
DD
V
EXT
V
SS
2
V
SS
V
SS
NF
V
SSQ
CS#
A5
A18
V
DD
NF
V
SSQ
NF
V
SS
TCK
3
V
DD
NF
V
DDQ
NF
V
SSQ
V
DD
A8
A12
V
SSQ
NF
V
DDQ
NF
V
DD
4
NF
V
SSQ
NF
V
DDQ
NF
A4
V
SS
A17
NF
V
DDQ
NF
V
SSQ
TDO
5
V
DDQ
NF
V
SSQ
NF
V
DDQ
A3
BA0
V
DD
V
DDQ
NF
V
SSQ
NF
V
DDQ
6
NF
V
DDQ
NF
V
SSQ
NF
REF#
V
SS
BA2
NF
V
SSQ
NF
V
DDQ
NF
7
V
REF
DM0
DK0#
DK0
MF
ZQ
CK#
CK
V
SS
DK1
DK1#
DM1
V
REF
8
DQ7
V
DDQ
DQ2
V
SSQ
QK0#
WE#
V
SS
BA3
QK1#
V
SSQ
DQ12
V
DDQ
DQ17
9
V
DDQ
DQ5
V
SSQ
QK0
V
DDQ
A1
BA1
V
DD
V
DDQ
QK1
V
SSQ
DQ15
V
DDQ
10
DQ8
V
SSQ
DQ3
V
DDQ
DQ1
A2
V
SS
A16
DQ9
V
DDQ
DQ13
V
SSQ
TDI
11
V
DD
DQ6
V
DDQ
DQ0
V
SSQ
V
DD
A6
A14
V
SSQ
DQ10
V
DDQ
DQ16
V
DD
12
V
SS
V
SS
DQ4
V
SSQ
A0
NC
1
A15
V
DD
QVLD
V
SSQ
DQ14
V
SS
TMS
13
RESET#
V
EXT
V
DD
A11
V
SS
A7
V
SS
A19
V
DDQ
DQ11
V
DD
V
EXT
V
SS
RESET Operation
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW. There are no restrictions for when it can go LOW. After RESET# goes LOW, it must
remain LOW for 100ns. During this time, the outputs are disabled, ODT (R
TT
) turns off
(High-Z), and the DRAM resets itself. Prior to RESET# going HIGH, at least 100 stable CK
cycles with NOP commands must be given to the RLDRAM. After RESET# goes HIGH,
the DRAM must be reinitialized as though a normal power-up was executed. All refresh
counters on the DRAM are reset, and data stored in the DRAM is assumed unknown af-
ter RESET# has gone LOW.
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
101
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.