Advance
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
Performing a TAP RESET
A reset is performed by forcing TMS HIGH (V
DDQ
) for five rising edges of
t
CK. This RE-
SET does not affect the operation of the device and may be performed while the device
is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
If JTAG inputs cannot be guaranteed to be stable during power-up it is recommended
that TMS be held HIGH for at least 5 consecutive TCK cycles prior to boundary scan
testing.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the RLDRAM 3 device test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded during the update-IR state of the TAP controller. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded with the IDCODE in-
struction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a bina-
ry 01 pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed be-
tween the TDI and TDO balls. This enables data to be shifted through the device with
minimal delay. The bypass register is set LOW (V
SS
) when the BYPASS instruction is exe-
cuted.
Boundary-Scan Register
The boundary-scan register is connected to all the input and bidirectional balls on the
device. Several balls are also included in the scan register to reserved balls. The device
has a 121-bit register.
The boundary-scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state.
The order in which the bits are connected is shown in Table 48 (page 110). Each bit cor-
responds to one of the balls on the RLDRAM package. The MSB of the register is con-
nected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR
state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the RLDRAM 3 and can be shifted out when the TAP controller is in the
shift-DR state. The ID register has a vendor code and other information described in
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
105
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