Advance
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM 3 device incorporates a serial boundary-scan test access port (TAP) for
the purpose of testing the connectivity of the device after it has been mounted on a
printed circuit board (PCB). As the complexity of PCB high-density surface mounting
techniques increases, the boundary-scan architecture is a valuable resource for inter-
connectivity debug. This port operates in accordance with IEEE Standard 1149.1-2001
(JTAG) with the exception of the ZQ pin. To ensure proper boundary-scan testing of the
ZQ pin, MR1[7] needs to be set to 0 until the JTAG testing of the pin is complete. Note
that upon power up, the default state of the MRS bit M1[7] is low.
The JTAG test access port utilizes the TAP controller on the device, from which the in-
struction register, boundary-scan register, bypass register, and ID register can be selec-
ted. Each of these functions of the TAP controller is described in detail below.
Disabling the JTAG Feature
It is possible to operate an RLDRAM 3 device without using the JTAG feature. To disable
the TAP controller, TCK must be tied LOW (V
SS
) to prevent clocking of the device. TDI
and TMS are internally pulled up and may be unconnected. They may alternately be
connected to V
DDQ
through a pull-up resistor. TDO should be left unconnected. Upon
power-up, the device will come up in a reset state, which will not interfere with the op-
eration of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK.
All the states in Figure 68 (page 104) are entered through the serial input of the TMS
ball. A 0 in the diagram represents a LOW on the TMS ball during the rising edge of TCK,
while a 1 represents a HIGH on TMS.
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can
be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. For informa-
tion on loading the instruction register, see Figure 68 (page 104). TDI is connected to
the most significant bit (MSB) of any register (see Figure 69 (page 104)).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the reg-
isters. The TDO output driver is only active during the Shift-IR and Shift-DR TAP con-
troller states. In all other states, the TDO ball is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any regis-
ter (see Figure 69 (page 104)).
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
102
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