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    MT46H16M32LF 参数 Datasheet PDF下载

    MT46H16M32LF图片预览
    型号： MT46H16M32LF
    PDF下载： 下载PDF文件 查看货源
    内容描述： 512MB ： X16 ， X32手机的低功耗DDR SDRAM特点 [512Mb: x16, x32 Mobile Low-Power DDR SDRAM Features]
    分类和应用： 动态存储器双倍数据速率手机
    文件页数/大小： 96 页 / 3106 K
    品牌： MICRON [ MICRON TECHNOLOGY ]
     浏览型号MT46H16M32LF的Datasheet PDF文件第1页浏览型号MT46H16M32LF的Datasheet PDF文件第2页浏览型号MT46H16M32LF的Datasheet PDF文件第3页浏览型号MT46H16M32LF的Datasheet PDF文件第4页浏览型号MT46H16M32LF的Datasheet PDF文件第6页浏览型号MT46H16M32LF的Datasheet PDF文件第7页浏览型号MT46H16M32LF的Datasheet PDF文件第8页浏览型号MT46H16M32LF的Datasheet PDF文件第9页  
    512Mb: x16, x32 Mobile LPDDR SDRAM
    Features
    List of Figures
    Figure 1: 512Mb Mobile LPDDR Part Numbering .............................................................................................. 2
    Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
    Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
    Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11
    Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12
    Figure 6: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 15
    Figure 7: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................. 16
    Figure 8: Typical Self Refresh Current vs. Temperature .................................................................................... 25
    Figure 9: ACTIVE Command .......................................................................................................................... 37
    Figure 10: READ Command ........................................................................................................................... 38
    Figure 11: WRITE Command ......................................................................................................................... 39
    Figure 12: PRECHARGE Command ................................................................................................................ 40
    Figure 13: DEEP POWER-DOWN Command ................................................................................................... 41
    Figure 14: Simplified State Diagram ............................................................................................................... 47
    Figure 15: Initialize and Load Mode Registers ................................................................................................. 49
    Figure 16: Alternate Initialization with CKE LOW ............................................................................................ 50
    Figure 17: Standard Mode Register Definition ................................................................................................. 51
    Figure 18: CAS Latency .................................................................................................................................. 54
    Figure 19: Extended Mode Register ................................................................................................................ 55
    Figure 20: Status Read Register Timing ........................................................................................................... 57
    Figure 21: Status Register Definition .............................................................................................................. 58
    Figure 22: READ Burst ................................................................................................................................... 61
    Figure 23: Consecutive READ Bursts .............................................................................................................. 62
    Figure 24: Nonconsecutive READ Bursts ........................................................................................................ 63
    Figure 25: Random Read Accesses .................................................................................................................. 64
    Figure 26: Terminating a READ Burst ............................................................................................................. 65
    Figure 27: READ-to-WRITE ............................................................................................................................ 66
    Figure 28: READ-to-PRECHARGE .................................................................................................................. 67
    Figure 29: Data Output Timing –
    t
    DQSQ,
    t
    QH, and Data Valid Window (x16) .................................................... 68
    Figure 30: Data Output Timing –
    t
    DQSQ,
    t
    QH, and Data Valid Window (x32) .................................................... 69
    Figure 31: Data Output Timing –
    t
    AC and
    t
    DQSCK .......................................................................................... 70
    Figure 32: Data Input Timing ......................................................................................................................... 72
    Figure 33: Write – DM Operation .................................................................................................................... 73
    Figure 34: WRITE Burst ................................................................................................................................. 74
    Figure 35: Consecutive WRITE-to-WRITE ....................................................................................................... 75
    Figure 36: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75
    Figure 37: Random WRITE Cycles .................................................................................................................. 76
    Figure 38: WRITE-to-READ – Uninterrupting ................................................................................................. 77
    Figure 39: WRITE-to-READ – Interrupting ...................................................................................................... 78
    Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 79
    Figure 41: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 80
    Figure 42: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81
    Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 82
    Figure 44: Bank Read – With Auto Precharge ................................................................................................... 85
    Figure 45: Bank Read – Without Auto Precharge .............................................................................................. 86
    Figure 46: Bank Write – With Auto Precharge .................................................................................................. 87
    Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 88
    Figure 48: Auto Refresh Mode ........................................................................................................................ 89
    Figure 49: Self Refresh Mode .......................................................................................................................... 91
    Figure 50: Power-Down Entry (in Active or Precharge Mode) ........................................................................... 92
    PDF: 09005aef83dd2b3e
    t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
    5
    Micron Technology, Inc. reserves the right to change products or specifications without notice.
    ©
    2009 Micron Technology, Inc. All rights reserved.

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