512Mb: x16, x32 Mobile LPDDR SDRAM
General Description
General Description
The 512Mb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-
access memory containing 536,870,912 bits. It is internally configured as a quad-bank
DRAM. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 col-
umns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by
512 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’s
134,217,728- bit banks are organized as 16,384 rows by 256 columns by 32 bits.
Note:
1. Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ should
be interpreted as any and all DQ collectively, unless specifically stated otherwise. Addi-
tionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower
byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the upper byte
(DQ[15:8]), DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes.
For DQ[7:0], DM refers to DM0 and DQS refers to DQS0. For DQ[15:8], DM refers to
DM1 and DQS refers to DQS1. For DQ[23:16], DM refers to DM2 and DQS refers to
DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to DQS3.
2. Complete functionality is described throughout the document; any page or diagram
may have been simplified to convey a topic and may not be inclusive of all require-
ments.
3. Any specific requirement takes precedence over a general statement.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
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