512Mb: x16, x32 Mobile LPDDR SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: Functional Block Diagram (x16)
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
Command
decode
Control
logic
Bank 2
Bank 3
Refresh
counter
Bank 1
Standard mode
register
Extended mode
register
Row-
address
Mux
Bank 0
row-
address
latch
and
decoder
Bank 0
memory
array
16
32
16
Data
Sense amplifiers
Read
latch
16
MUX
DRVRS
DQS
generator
2
DQ[15:0]
CK
Input
registers
2
2
2
16
16
2
16
16
16
RCVRS
LDM,
UDM
DQS
LDQS,
UDQS
COL 0
2
Address
BA0, BA1
Address
register
2
Bank
control
logic
I/O gating
DM mask logic
32
Mask
32
Write
FIFO
and
drivers
CK
out
CK
in
4
32
Data
2
Column
decoder
Column-
address
counter/
latch
1
CK
COL 0
2
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
9
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