256Mb: x4, x8, x16 DDR SDRAM
Commands
Commands
Tables 20 and 21 provide a quick reference of available commands. Two additional Truth
Tables—Table 22 on page 44 and Table 23 on page 45—provide current state/next state
information.
Table 20:
Truth Table 1 – Commands
CKE is HIGH for all commands shown except SELF REFRESH; All states and sequences not shown are illegal or
reserved
Function
DESELECT
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column and start READ burst)
WRITE (select bank and column and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LOAD MODE REGISTER
Notes:
CS#
H
L
L
L
L
L
L
L
L
RAS#
X
H
L
H
H
H
L
L
L
CAS#
X
H
H
L
L
H
H
L
L
WE#
X
H
H
H
L
L
L
H
L
Address
X
X
Bank/row
Bank/col
Bank/col
X
Code
X
Op-code
Notes
1. DESELECT and NOP are functionally interchangeable.
2. BA[1:0] provide bank address and A[n:0] (128Mb:
n
= 11; 256Mb and 512Mb:
n
= 12; 1Gb:
n
= 13) provide row address.
3. BA[1:0] provide bank address; A[i:0] provide column address, (where Ai is the most signifi-
cant column address bit for a given density and configuration, see Table 2 on page 2) A10
HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto
precharge feature.
4. Applies only to READ bursts with auto precharge disabled; this command is undefined (and
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA[1:0] determine which bank is precharged. A10 HIGH: all banks are precharged
and BA[1:0] are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing while in self refresh mode, all inputs and
I/Os are “Don’t Care” except for CKE.
8. BA[1:0] select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA[1:0] are reserved). A[n:0] provide the op-code to be written to the selected
mode register.
Table 21:
Truth Table 2 – DM Operation
Used to mask write data, provided coincident with the corresponding data
Name (Function)
Write enable
Write inhibit
DM
L
H
DQ
Valid
X
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
