256Mb: x4, x8, x16 DDR SDRAM
Commands
Table 25:
CKE
n-1
L
L
H
Truth Table 5 – CKE
Notes 1–6 apply to the entire table; Notes appear below
CKE
n
L
H
L
Current State
Power-down
Self refresh
Power-down
Self refresh
All banks idle
Bank(s) active
All banks idle
Notes:
Command
n
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
See Table 20 on page 43
Action
n
Maintain power-down
Maintain self refresh
Exit power-down
Exit self refresh
Precharge power-down entry
Active power-down entry
Self refresh entry
Notes
H
H
1. CKE
n
is the logic state of CKE at clock edge
n;
CKE
n-1
was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge
n.
3. COMMAND
n
is the command registered at clock edge
n,
and ACTION
n
is a result of COM-
MAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
HIGH until after the read postamble time (
t
RPST); for a WRITE, CKE must stay HIGH until the
write recovery time (
t
WR) has been met.
6. Once initialized, including during self refresh mode, V
REF
must be powered within the spec-
ified range.
7. Upon exit of the self refresh mode, the DLL is automatically enabled. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurring during the
t
XSNR period.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in prog-
ress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A0–An (see "REGISTER DEFINITION" on page
executable command cannot be issued until
t
MRD is met.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
