PRELIMINARY
1Gb : x4, x8, x16
DDR SDRAM
for each burst type in the Operation section of this
data sheet. The user must not issue another command
to the sam e bank until the precharge tim e (tRP) is
completed.
JEDEC requirement by one clock. This maximum
absolute interval is to allow future support for DLL
updates internal to the DDR SDRAM to be restricted to
AUTO REFRESH cycles, without allowing excessive
t
drift in AC between updates.
Although not a JEDEC requirem ent, to provide for
future functionality features, CKE must be active
(High) during the AUTO REFRESH period. The AUTO
REFRESH period begins when the AUTO REFRESH
command is registered and ends tRFC later.
BURST TERMINATE
The BURST TERMINATE com m and is used to trun-
cate read bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE comm and will be truncated, as
shown in the Operation section of this data sheet. The
open page which the READ burst was terminated from
remains open.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an
AUTO REFRESH com m and except CKE is disabled
(LOW). The DLL is automatically disabled upon enter-
ing SELF REFRESH and is automatically enabled upon
exiting SELF REFRESH (A DLL reset and 200 clock
cycles must then occur before a READ command can
be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. VREF voltage is also required
for the SELF REFRESH full duration.
AUTO REFRESH
AUTO REFRESH is used during norm al operation of
the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) refresh in FPM/ EDO DRAMs. This com-
m and is nonpersistent, so it m ust be issued each tim e
a refresh is required. All banks m ust be idle before an
AUTO REFRESH com m and is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 1Gb DDR
SDRAM requires AUTO REFRESH cycles at an average
interval of 7.8125µs (maximum).
The procedure for exiting self refresh requires a
sequence of commands. First, CK and CK# must be
stable prior to CKE going back HIGH. Once CKE is
HIGH, the DDR SDRAM must have NOP commands
issued for tXSNR because time is required for the com-
pletion of any internal refresh in progress. A sim ple
algorithm for m eeting both refresh and DLL require-
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH com m ands can be posted to any
given DDR SDRAM, m eaning that the m axim um abso-
lute interval between any AUTO REFRESH com m and
and the next AUTO REFRESH command is 9 x 7.8125µs
(70.3µs). Note the JEDEC specifications only allows 8 x
7.8125µs, thus the Micron specification exceeds the
t
m ents is to apply NOPs for XSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
17
MICRON [ MICRON TECHNOLOGY ]
