PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 11: READ Burst
T0
CK#
CK
COMMAND
ADDRESS
READ
Bank a,
Col
n
NOP
NOP
NOP
NOP
NOP
T1
T2
T2n
T3
T3n
T4
T5
CL = 2
DQS
DQ
T0
CK#
CK
COMMAND
ADDRESS
READ
Bank
a,
Col
n
NOP
NOP
NOP
NOP
NOP
DO
n
T1
T2
T2n
T3
T3n
T4
T5
CL = 2.5
DQS
DQ
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO
n
= data-out from column
n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO
n.
4. Shown with nominal
t
AC,
t
DQSCK, and
t
DQSQ.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
