PRELIMINARY
1Gb : x4, x8, x16
DDR SDRAM
command, where x equals the number of desired data
elem ent pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 12 on page 22. A
READ command can be initiated on any clock cycle
following a previous READ com m and. Nonconsecutive
read data is shown for illustration in Figure 13 on
page 23. Full-speed random read accesses within a
page (or pages) can be performed as shown in
Figure 14 on page 24.
Data from any READ burst may be truncated with a
BURST TERMINATE command, as shown in Figure 15
on page 25. The BURST TERMINATE latency is equal
to the read (CAS) latency, i.e., the BURST TERMINATE
command should be issued x cycles after the READ
command, where x equals the number of desired data
elem ent pairs (pairs are required by the 2n-prefetch
architecture).
READs
READ bursts are initiated with a READ command, as
shown in Figure 10 on page 20.
The starting colum n and bank addresses are pro-
vided with the READ com m and and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst.
NOTE: For the READ commands used in the follow-
ing illustrations, auto precharge is disabled.
During READ bursts, the valid data-out elem ent
from the starting column address will be available fol-
lowing the CAS latency after the READ command.
Each subsequent data-out element will be valid nomi-
nally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 11 on page 21
shows general timing for each possible CAS latency
setting. DQS is driven by the DDR SDRAM along with
output data. The initial LOW state on DQS is known as
the read preamble; the LOW state coincident with the
last data-out elem ent is known as the read postamble.
Upon completion of a burst, assuming no other
com m ands have been initiated, the DQs will go High-
Data from any READ burst must be completed or
truncated before a subsequent WRITE comm and can
be issued. If truncation is necessary, the BURST TER-
MINATE command must be used, as shown in
Figure 16 on page 26. The tDQSS (NOM) case is shown;
the tDQSS (MAX) case has a longer bus idle time.
t
(tDQSS [MIN] and DQSS [MAX] are defined in the sec-
t
Z. A detailed explanation of DQSQ (valid data-out
tion on WRITEs.)
skew), tQH (data-out window hold), the valid data win-
dow are depicted in Figure 38 on page 60 and Figure 39
A READ burst m ay be followed by, or truncated with,
a PRECHARGE com m and to the sam e bank provided
that auto precharge was not activated. The PRE-
CHARGE com m and should be issued x cycles after the
READ command, where x equals the number of
desired data elem ent pairs (pairs are required by the
2n-prefetch architecture). This is shown in Figure 17
on page 27. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
t
on page 61. A detailed explanation of DQSCK (DQS
transition skew to CK) and AC (data-out transition
skew to CK) is depicted in Figure 40 on page 62.
t
Data from any READ burst may be concatenated
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be m aintained. The first data elem ent from the
new burst follows either the last element of a com-
pleted burst or the last desired data element of a longer
burst which is being truncated. The new READ com-
mand should be issued x cycles after the first READ
t
t
issued until both RAS and RP has been met. Note that
part of the row precharge tim e is hidden during the
access of the last data elements.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
19
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