PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 27: WRITE to Precharge – Interrupting
T0
CK#
CK
COMMAND
WRITE
NOP
NOP
t
WR
NOP
PRE
8
NOP
t
RP
Bank,
(a or
all)
NOP
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
ADDRESS
t
DQSS (NOM)
Bank
a,
Col
b
t
DQSS
DQS
DQ
DM
t
DQSS (MIN)
t
DQSS
DI
b
DQS
DQ
DM
t
DQSS (MAX)
t
DQSS
DI
b
DQS
DQ
DM
DI
b
DON’T CARE
NOTE:
TRANSITIONING DATA
1. DI
b
= data-in for column
b.
2.
3.
4.
5.
6.
7.
8.
Subsequent element of data-in is applied in the programmed order following DI
b.
An interrupted burst of 8 is shown; two data elements are written.
t
WR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T4 and T4n (nominal case) to register DM.
If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n.
PRE = PRECHARGE command.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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