PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 23: WRITE to READ - Uninterrupting
T0
CK#
CK
COMMAND
WRITE
NOP
NOP
NOP
t
WTR
READ
NOP
NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
T6n
ADDRESS
t
DQSS (NOM)
Bank
a,
Col
b
t
DQSS
Bank
a,
Col
n
CL = 2
DQS
DQ
DM
t
DQSS (MIN)
t
DQSS
DI
b
DO
n
CL = 2
DQS
DQ
DM
t
DQSS (MAX)
t
DQSS
DI
b
DO
n
CL = 2
DQS
DQ
DM
DI
b
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI
b
= data-in for column
b, DO n =
data-out for column
n.
Three subsequent elements of data-in are applied in the programmed order following DI
b.
An uninterrupted burst of 4 is shown.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in
which case
t
WTR is not required and the READ command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
2.
3.
4.
5.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
