PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 25: WRITE to READ - Odd Number of Data, Interrupting
T0
CK#
CK
COMMAND
WRITE
NOP
NOP
t
WTR
READ
NOP
NOP
NOP
T1
T1n
T2
T2n
T3
T3n
T4
T5
T5n
T6
T6n
ADDRESS
t
DQSS (NOM)
Bank
a,
Col
b
t
DQSS
Bank
a,
Col
n
CL = 2
DQS
DQ
DM
t
DQSS (MIN)
t
DQSS
DI
b
DO
n
CL = 2
DQS
DQ
DM
t
DQSS (MAX)
t
DQSS
DI
b
DO
n
CL = 2
DQS
DQ
DM
DI
b
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI
b
= data-in for column
b, DO n =
data-out for column
n.
2.
3.
4.
5.
6.
An interrupted burst of 4 is shown; one data element is written.
WTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T1n, T2, and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 - T3n because the READ command would not mask these data
elements.
t
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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