PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 14: I
DD
Specifications and Conditions (x4, x8)
0°C
£
T
A
£
+70°C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V
Notes: 1–5, 10, 12, 14; notes appear on page 54-57; See also Table 16, I
MAX
PARAMETER/CONDITION
SYMBOL
-75
145
UNITS
mA
NOTES
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
I
DD
0
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA; Address
and control inputs
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK (MIN);
CKE = (LOW)
I
DD
1
180
mA
I
DD
2P
10
mA
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock
cycle. V
IN
= V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active
;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
I
DD
2F
60
mA
I
DD
3P
I
DD
3N
30
45
mA
mA
OPERATING CURRENT: Burst = 2;
Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN);
I
OUT
= 0mA
I
DD
4R
200
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank
active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
t
AUTO REFRESH BURST CURRENT:
RC =
t
RFC(MIN)
t
I
DD
4W
210
mA
I
DD
5
I
DD
5A
I
DD
6
I
DD
7
SELF REFRESH CURRENT: CKE
£
0.2V
RFC = 7.8us,
Standard
330
10
9
485
mA
mA
mA
mA
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge,
t
RC = minimum
t
RC allowed;
t
CK =
t
CK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
