PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 42: Initialize And Load Mode Registers
V
DD
((
))
((
))
V
DD
Q
V
TT
1
V
REF
t
VTD
1
((
))
((
))
T0
CK#
CK
((
))
((
))
T1
((
))
((
))
Ta0
((
))
((
))
Tb0
((
))
((
))
Tc0
((
))
((
))
Td0
((
))
((
))
Te0
((
))
((
))
Tf0
t
CH
t
IS
t
IH
t
CL
CKE
LVCMOS
LOW LEVEL
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIS
COMMAND
6
((
))
((
))
((
))
((
))
tIH
PRE
t
CK
((
))
((
))
((
))
((
))
NOP
LMR
((
))
((
))
((
))
((
))
LMR
((
))
((
))
((
))
((
))
PRE
((
))
((
))
((
))
((
))
AR
((
))
((
))
((
))
((
))
AR
((
))
((
))
((
))
((
))
ACT5
DM
tIS
A0-A9,
A11, A12, A13
((
))
((
))
((
))
((
))
tIH
((
))
((
))
CODE
CODE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
A10
((
))
((
))
ALL BANKS
tIS
((
))
((
))
((
))
((
))
tIH
((
))
((
))
((
))
((
))
CODE
CODE
tIS
tIH
((
))
((
))
((
))
((
))
ALL BANKS
tIS
tIH
BA0 = L,
BA1 = L
t
IS
t
IH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
BA0, BA1
((
))
((
))
BA0 = H,
BA1 = L
BA
DQS
DQ
T = 200µs
((
))
((
))
High-Z
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
tMRD
tRP
((
))
((
))
((
))
((
))
tRFC
((
))
((
))
tRFC
5
Power-up: V
DD
and CK stable
tRP
tMRD
Load Extended
Mode Register
200 cycles of CK
3
Load Mode
Register
2
DON’T CARE
NOTE:
1. V
TT
is not applied directly to the device; however,
t
VTD should be greater than or equal to zero to avoid device latch-up.
V
DD
Q, V
TT
, and V
REF
, must be equal to or less than V
DD
+ 0.3V. Alternatively, V
TT
may be 1.35V maximum during power up,
even if V
DD
/V
DD
Q are 0V, provided a minimum of 42 ohms of series resistance is used between the V
TT
supply and the input
pin. Once initialized, V
REF
must always be powered with in specified range.
2. Reset the DLL with A8 = H while programming the operating parameters.
3.
t
MRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can
be issued.
4. The two AUTO REFRESH commands at Td0 and Te0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any
bank. If another LMR command is issued, the same operating parameter, previously issued, must be used.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE com-
mand, RA = Row Address, BA = Bank Address.
-75
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
IH
F
t
IS
F
MIN
0.45
0.45
7.5
10
.90
.90
MAX
0.55
0.55
13
13
UNITS
t
CK
t
CK
ns
ns
ns
ns
SYMBOL
t
IH
S
t
IS
S
t
MRD
t
RFC
t
RP
t
VTD
MIN
1
1
15
120
20
0
-75
MAX
UNITS
ns
ns
ns
ns
ns
ns
13
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
